The invention relates to memory arrangements for temporary data storage of the type currently designated as "first in-first out" or "FIFO". It is suitable for use each time a buffer memory is necessary since there is no time coincidence between input signals representative of external events and the times for use of such signals. Examples of such use are data mixing, curve smoothening, conversion from an arrival frequency to a use frequency, and multiplexing. Two types of FIFO arrangements are presently used. In a first type, the data circulate along a stack of registers. In that embodiment, complete asynchronism between the writing and read out operations is possible. On the other hand, that arrangement has drawbacks: the storage capacity is severely limited. There is a substantial propagation time from the input to the output and that time increases when the storage capacity increases. In the other type, the FIFO arrangement includes a random access memory associated with a control logic. The storage capacity may be substantially increased, but complete asynchronism between the writing and reading operations is lost.
It is an object of the invention to provide a FIFO arrangement including a random access memory or RAM which is improved in that the access time is the same whatever the storage capacity while there is no need for a specific time relationship betwen reading and writing operations.
According to the invention, there is provided a FIFO arrangement for temporary data storage which includes:
a random access memory having an input and an output,
a control system for said random access memory,
a first and a second output buffer register connected in series relation to the output of said random access memory,
an input buffer register connected to the output of said random access memory,
wherein said control system includes: PA1 first means for storing write request one at the time, PA1 second means for storing the condition of said input buffer register, said second means being operatively associated with additional means arranged for setting said second storing means in response to the presence of an external writing request stored in said first storing means when said second storing means are in a condition indicating that said input buffer register is empty, PA1 third means for generating an internal writing request signal and directing it to said random access memory when said second storing means indicate that said input buffer register is loaded and as long as said random access memory has not acknowledged said internal writing request, said third means being arranged and connected to reset said second storing means into a condition indicating that said input buffer register is empty when said writing request has been acknowledged, PA1 third storing means for storing the condition of said first output buffer register, PA1 fourth storing means for storing the condition of said second buffer register, PA1 supplemental means for generating an internal reading request and directing it to said random access memory when said third storing means are in a condition indicating that the first output buffer register is empty and as long as said reading request has not been acknowledged, and for resetting said third storing means into a condition indicating that said first output register is loaded as soon as the reading request has been acknowledged, PA1 a unit for setting said fourth storing means when the third storing means indicate that the first output register is loaded and said fourth storing means indicate that the second output register is empty, said unit being connected to simultaneously reset said third storing means into a condition indicating that said first output buffer register is empty, PA1 and means for setting said fourth storing means when the latter indicates said second output buffer register is loaded and after an external signal representative of a request for reading out of the said second output buffer register has been delivered,
a first control logic for controlling operation of said input buffer register, having:
a second control logic having:
and a logic circuit for solving conflicts between an internal writing-in request and an internal reading-out request.
European Patent Application No. 00 48586 (SONY CORPORATION) discloses an arrangement comprising a random access memory associated with one input register and two cascaded output registers. However, such buffer registers are not functionally equivalent to the registers in the present invention and are not similarly controlled. Their purpose is to enable reading-out from the random access memory in synchronism with a read signal which is asynchronous with the write signals. That prior art arrangement was designed for processing television signals prior to recording on a VTR, such processing involving a frequency conversion. The control logic associated with the buffer registers is not adapted to handle asynchronism between randomly received write-in and read-out signals and was not designed to do so.
The invention will be better understood from the following description of a preferred embodiment and from the comparison which is made with the prior art. The description refers to the accompanying drawings.